U.S. Pat. No. 7,486,145 discusses circuits and methods for implementing programmable sub-integer N frequency dividers for use in, e.g., frequency synthesizer applications, providing glitch free outputs signals with minimal fractional spurs. Phase-rotating sub-integer N frequency dividers are programmable to provide multi-modulus division with a wide range of arbitrary sub-integer division ratios.
Phase-locked loop (PLL) circuits are critical components commonly implemented in various communications systems to provide, e.g., LO (local oscillator) signals for transceiver circuits, clock signals for data-recovery circuits, etc. In general, a PLL circuit uses feedback to maintain an outputted signal of the PLL in a specific phase relationship with a reference input signal of the PLL, as is well known in the art. When the output frequency of the PLL is equal to the frequency of the reference input signal, the PLL is in a “locked” condition.
PLL circuits are commonly implemented to construct frequency synthesizer circuits for use in various applications in which it is desirable to generate one or more of a plurality of new clock signals based on a reference clock signal. Essentially, a frequency synthesizer is a PLL that employs a programmable frequency divider in the PLL feedback loop. By way of example, FIG. 1 is a high-level schematic illustration of a conventional PLL frequency synthesizer circuit 10. The PLL frequency synthesizer 10 comprises a PFD (phase-frequency detector) circuit 11, a charge pump 12, a loop filter 13, a VCO (voltage controlled oscillator) circuit 14, and a frequency divider 15 in a PLL feedback loop.
In general, the PLL frequency synthesizer 10 generates an outputted signal Vout having a frequency fout that is some multiple N of the frequency fin of a reference clock signal Ref_CLK, where fout=N·fRef. The PFD circuit 11 receives the input reference signal Ref_CLK and a feedback signal fDiv and compares the phases of such signals. The PFD 11 generates a slowly varying phase error outputted signal that is a function of the phase difference between the reference and feedback signals. The charge pump 12 operates in conjunction with the PFD (1) to generate an output current signal based on the detected phase difference. The loop filter 13 low-pass filters the phase error signal generated by the PFD 11 and CP 12 and outputs a control voltage to the VCO 14. In general, the charge pump 12 and loop filter 13 operate to amplify and filter the phase error signal output from the PFD 11 according to a filter transfer function that is selected to achieve desired loop characteristics such as gain, bandwidth, frequency response, etc., in a manner well known in the art.
The control voltage output from the loop filter 13 is a control signal that is input to a control port of the VCO 14. The VCO 14 may be a voltage controlled LC tank oscillator where frequency tuning is achieved based on the voltage level of the control signal output from the loop filter 13. The control signal voltage incrementally increases or decreases so as to drive the VCO 14 output frequency fout in the direction of N·fRef. The outputted signal Vout is fed back to the PFD 11 via the frequency divider circuit 15, which divides the VCO output frequency by the dividing factor N to generate a low frequency signal fDiv, where fRef=fDiv when the PLL frequency synthesizer achieves the desired “locked” state.
As noted above, a fundamental function of a PLL is to lock the phase of the outputted signal to the phase of the reference signal. In general, standard Laplace transform theory can be used to show that the PLL tracks the input phase within a certain loop bandwidth, acting as a low-pass filter with respect to the carrier frequency to phase fluctuations on the input reference signal Ref_CLK. From a phase-noise perspective, this means that the phase noise of Ref_CLK is passed within the bandwidth of the loop and actually amplified by the division factor (20·log 10(N)). Similarly, the combined phase noise from the frequency divider 15, the PFD 11, charge pump 12, and the loop filter 13 is amplified by the division factor N within the loop bandwidth.
Conversely, phase noise from the VCO 14 is rejected within the bandwidth of the loop, but is passed outside the bandwidth. In other words, the PLL essentially acts as a high-pass filter with respect to the carrier frequency to phase fluctuations on the VCO 14. In addition to setting the phase-noise profile, the loop bandwidth also determines the locking time of the PLL through a converse relationship, i.e., BW˜1/τ. It is noted that the bandwidth cannot be set as arbitrarily large, as loop instabilities can result. Therefore, as a rule of thumb, the loop bandwidth is limited to about an order of magnitude less than the Ref_CLK frequency.
In general, the PLL frequency synthesizer 10 may be implemented as an “integer-N” synthesizer or “fractional-N” synthesizer, depending on the frequency dividing factor N of the frequency divider circuit 15. In particular, with an “integer-N” architecture, the dividing factor N of the frequency divider 15 is selected such that the output frequency of the VCO is only an integer multiple of the reference frequency. Consequently, the reference frequency cannot be higher in frequency than the desired step size (channel resolution). An integer-N PLL synthesizer framework is advantageous in terms of having a simple architecture/design and having fewer spurs in the output spectrum.
On the other hand, a fractional-N synthesizer allows frequencies equal to fractional multiples of the reference frequency fRef to be synthesized. That is, the dividing factor N of the frequency divider 15 can be a fractional number, which, for a given channel resolution, allows the reference clock to be at a higher frequency. A fractional-N type synthesizer offers several advantages over integer-N synthesizers. First, the loop bandwidth can be increased, since the bandwidth of the loop is usually confined to be about fRef/10 for stability purposes. The larger loop bandwidth results in suppression of the VCO phase noise over a larger range. Secondly, the higher fREF means that the division factor is smaller, resulting in reduced in-band phase noise.
Conventional fractional-N synthesizers can be implemented using various techniques known in the art. For instance, a fractional-N synthesizer may be built using dual-modulus frequency dividers, where the modulus of the divider is switched between two division ratios, N and N+1, whereby the average dividing factor is determined based on the ratio of the time in a predetermined period during which N and N+1 divisors were applied. For example, a dual-modulus divide-by-128/129 frequency divider can be controlled such that it divides by 128 97% of the time and by 129 3% of the time. The overall dividing factor is then 128.03.
With this technique, if the switching between the two division ratios is periodic, then a fractional spur will result, occurring at multiple frequencies of fRef/100 for this example. Consequently, fractional-N synthesizers typically employ delta-sigma (Δ-Σ) modulators to vary the modulus in a random fashion and to shape it to resultant quantization noise to fall outside of the passband of the PLL. For certain applications, however, the channel resolution is not significantly tight to warrant a full-blown Δ-Σ synthesizer, although it is still desirable to realize fractional division ratios.
Another technique for implementing a fractional-N synthesizer, is based on a phase-switched frequency divider architecture, where different divide factors of a multi-modulus prescaler are realized using a phase rotator or phase selector to switch between different phase states of a plurality of phase shifted signals generated by the frequency divider, e.g., 4 signals having the same frequency but phases shifted by 0, π/2, π and 3/2·π radians. For instance, in most implementations, switching is performed by transitioning from one phase state to a next phase state with is π/2 radians lagging in phase (e.g., from I to Q, from I+Q to Q−I, etc.), resulting in a scaling of the period by 1.25. Division by one value can be achieved by selecting one of four phase states while division by another value can be achieved by continuously rotating among the phase states at every cycle.